Clock networks are an important part of implementing circuits in integrated circuit devices. Because significant power is consumed by routing clock signals in an integrated circuit, routing a signal at a half clock rate can result in a reduction in power. Further, a clock signal can be altered as it is routed in a clock network of the integrated circuit. For example, duty-cycle distortion (DCD) associated with rising and falling edges of a clock signal occurs due to the difference in rising and falling edge signal propagation in the clock network. There is generally a difference between the strength of a PMOS transistor (used for a 0 to 1 transition) and strength of an NMOS transistor (used for a 1 to 0 transition). This variation is largely due to materials used in the device and physical layout variation. Therefore, a rising edge and a falling edge that is driven from a common node will have different propagation times to the next buffer. The difference between rising and falling edge propagation will accumulate at each stage, creating distortion in the duty cycle of the clock signal.
When using both rising and falling edges to register data using a clock signal for example, there is a time penalty (either positive or negative) between consecutive rising and falling edges as a result of duty-cycle distortion. When only using one clock edge, the duty-cycle distortion can be ignored because the clocking functions are aligned with one edge. But with dual-edge clocking, duty-cycle distortion will add time to odd edge clock skew and subtract time from even edge clock skew, or vice versa, depending on rising/falling delay propagation ratio. As a result, duty-cycle distortion reduces the operating speed of the integrated circuit.
Accordingly, improved circuits for and methods of reducing power consumed by routing clock signals in an integrated circuit are desired.